When I first started building FPGA designs, I would check for zero within Unless you really know what you are doing … don’t This will cause you all kinds of grief, either leading you to an unreliableĭesign, or forcing you to deal with multiple clock domains, clock domain How shall you make your logic work only once in all those clocks?Īs a first rule, do not drive your logic like this: always ( posedge counter ) begin // DON'T DO THIS end The problem with the simple clock dividers above is that the clock signal is Nīits wide, and the top bit may be one for many clocks and zero for many clocks. Have divided your clock by whatever value you set THRESHOLD to be. reg counter always ( posedge i_clk ) if ( counter < THRESHOLD - 1'b1 ) counter <= counter + 1'b1 else counter <= 0 Īs before, you can then use counter as an LED driver, and you will This is easily done withĪ more generic clock divider circuit. You’d then need toĭivide it by 10M if you wanted to get a 10Hz clock. Suppose for example that your system clock were at 100MHz.

Since these are not the result of dividing your clockīy 2^N, a different approach is necessary. Hence, if you attach an LED to counter you’ll have the slower clockĪ very common beginners task is to create a 1kHz, 100Hz, or even a 10 Hz clockįrom your input clock. Using this approach, your clock will be nicely divided by an even 2^N.

reg counter always ( posedge i_clk ) counter <= counter + 1'b1 It’s just too simple and too easy to build to ignore. The first approach I will use to timing events is usually a clock divider. Here we’ll discuss a couple ways to create the timing you need. Require a logic generated clock, I2C controllers have some maximum limit theyĬan communicate at, UART controllers run at some user defined baud rate …Įverything wants to communicate at a carefully controlled speed. Within an FPGA, everything is based upon event based timing.

Clock divider verilog